◆Low voltage and low power operations:
EC24C1024:VCC = 1.8V to 5.5V
◆Maximum Standby current < 1µA.
◆256 bytes page write mode.
◆Partial page write operation allowed.
◆Internally organized: 131,072 X 8 (1024K).
◆Standard 2-wire bi-directional serial interface.
◆Schmitt trigger, filtered inputs for noise protection.
◆Self-timed programming cycle (5ms maximum).
◆ Automatic erase before write operation.
◆Write protect pin for hardware data protection.
◆High reliability: typically 1,000,000 cycles endurance.
◆40 years data retention.
◆Industrial temperature range (-40°C to 85°C).
◆Standard 8-pin DIP/SOP Pb-free packages.
The EC24C1024 series are 1,048,576 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 131,072 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, and 8-lead SOP packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
All three packaging types come in Pb-free certified.
EC24C XXXX XX X X
R = Tape & Reel
T = Tube
1024 = 1024K-bit
G = Green
M1= SOP 8L
P1 = DIP 8
1. 1024 is the memory of production.
2. LLLLL is the last five numbers of wafer lot number
3. YYWW is Date Code.
4. T is tracking Code ,T=X
Absolute Maximum Ratings
Industrial operating temperature: -40℃ to 85℃
Storage temperature: -50℃ to 125°C
Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V
Maximum voltage: 8V
ESD Protection on all pins >2000V
＊Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. Functional operation of the device at conditions beyond those listed in the specification is not
guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The EC24C1024 device has a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level.
The EC24C1024 devices have 512 pages respectively. Since each page has 256 bytes, random word addressing to EC24C1024 will require 17 bits data word addresses.
A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below.
(B) START CONDITION
With SCL VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.
(C) STOP CONDITION
With SCL VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command.
A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish (see Figure 1).
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9 serial clock
after each word.
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.
Figure 1: Timing diagram for START and STOP conditions
Figure 2: Timing diagram for output ACKNOWLEDGE
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command.The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next two bits are device address bits.These two device address bits (5thand 6th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th and 6th ) as noted below. The seventh bit of the device address (P0) is a memory page address bit. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.
(A) BYTE WRITE
A write operation requires the seventh bit of the device address (P0) and two 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internally- timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3).
(B) PAGE WRITE
The 1024K EEPROM are capable of 256-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 255 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a
STOP condition (see Figure 4). The lower 8 bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten.
(C) ACKNOWLEDGE POLLING
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9 th clock cycle.
The read command is similar to the write command except the. 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows:
(A) CURRENT ADDRESS READ
The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro- controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an
ACKNOWLEDGE signal on the 9 th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18 th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see Figure 5).
(B) SEQUENTIAL READ
The sequential read is very similar to current address read. The micro-controller issues a START bit nd a valid device address word with read/write bit (8 th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9 th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18 th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27 th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential
read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro- controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (figure 6).
(C) RANDOM READ
Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START th acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 7).
Clock frequency, SCL
Clock pulse width low
Clock pulse width high
Noise suppression time
Clock low to data out
Time the bus must be
free before a new
transmission can start
START hold time
START set-up time
Data in hold time
Data in set-up time
Input rise time
Input fall time
STOP set-up time
Date out hold time
Write cycle time
Supply read current
VCC @ 5.0V SCL = 400 kHz
Supply write current
VCC @ 5.0V SCL = 400 kHz
VCC @ 1.8V, VIN = VCC or VSS
VCC @ 2.5V, VIN = VCC or VSS
VCC @ 5.0V, VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
Input low level
VCC × 0.3
Input high level
VCC × 0.7
VCC + 0.5
Output low level
VCC @ 3.0V, IOL = 2.1 mA
Output low level
VCC @ 1.8V, IOL = 0.15 mA
DIP8 Package Outline Dimensions
Dimensions In Millimeters
Dimensions In Inches
SOP8 Package Outline Dimensions
Dimensions In Millimeters
Dimensions In Inches